Kuaishou AI Infra campus hire (3)

This role targets optimization on heterogeneous NV and AMD platforms, covering AI compilers, model deployment and inference optimization, operator optimization, high-performance operator generation, TVM, Triton, graph optimization, quantization, and related areas.

Job responsibilities

1. Join technical design and development of AI-compiler projects; use parallel-compute optimization, architecture design, sparsity optimization, and heterogeneous scheduling on CPU, GPU, DSP, and NPU to build a high-performance heterogeneous AI inference engine and compiler.
2. For search, recommendation, ads, audio/video, and large-model scenarios, optimize compute-graph execution efficiency for training and inference.
3. Work closely with algorithm teams on joint algorithm–system optimization for key projects.

Requirements (any one is enough)

1. Experience with the LLVM toolchain and writing optimization Passes.
2. Strong C++, solid data structures and algorithms, familiarity with computer architecture and x86 assembly, some Python.
3. Familiarity with XLA, MLIR, TVM, Triton, TensorRT and related experience preferred.
4. Strong HPC optimization on CPU (ARM/x86) or GPU (Intel/Nvidia/AMD); deep computer-architecture understanding; familiarity with parallel-compute, memory-access, and low-bit compute optimization.
5. Understand basic deep-learning algorithms, common neural-net architectures and operator math; know at least one training framework (for example PyTorch, TensorFlow) and how to parse its model files.
6. Experience writing and optimizing CPU/GPU operator kernels; familiarity with CUDA.
7. Can solve problems independently, abstract and split business logic cleanly, and work well in a team.
8. Know mainstream AIGC model ideas; AIGC acceleration experience preferred.